Transforming DRC Closure At Advanced Nodes

If you’re working on SoCs at 2 nm or below, you know DRC is a different beast these days. Early in the design, it’s common for DRC runs to dump hundreds of millions—or even billions—of violations at your feet. And that’s when everything is changing fast: block interfaces aren’t fixed and constraints are shifting with every new iteration. Making sense of these massive result sets, figuring out what to fix first and keeping everyone coordinated is no small task.

The old way—waiting for every check to finish before you can even start looking at results—just doesn’t cut it anymore. When analysis only starts after a long, overnight run, teams waste precious time in a cycle of “run, then debug, then re-run” with bottlenecks at every stage.

So what’s the answer?

Getting closure at advanced nodes now means moving to real-time, AI-powered analysis that fits the way engineers work. You need workflows where DRC results show up as the job runs, with helpers that cut down the noise and organize what needs fixing. Instead of being buried in data, teams get straight to the root of problems and work together—making closure possible on today’s schedules and scale. Figure 1 shows an interactive dashboard that allows engineers to identify and address DRC issues as soon as they are reported, even before the full DRC run completes.

Fig. 1: The user interface of an AI-guided DRC analysis platform called Calibre Vision AI.

Instance-complete analysis: Don’t miss violations hiding in the hierarchy

In traditional DRC flows, verification tools often limit how many violations get reported as a way to prevent slow loading and downstream review. You might only see a few thousand errors per rule or per block, even if the real count is much higher. This is mostly a practical compromise: older tools and formats (like ASCII) can struggle with huge outputs and teams would need to run the check again and again to see the full scope.

An instance-complete DRC analysis and debug catches everything: It records every violation—no matter how deep or repeated the block is, no matter how many instances you have. You get the whole error picture the first time, for every part of the chip. Instead of discovering “surprise” errors after several runs, you see the whole picture from the start, for every part of your chip. Fixing the real issues early saves precious debug cycles—and, honestly, a lot of frustration.

How is it possible?

1. Use of modern file formats (primarily OASIS) and optimized result storage.
2. Hierarchical awareness treats every cell, block and its instances individually—nothing is lost or compressed away.
3. Scalable algorithms built to process and reduce mountains of data into manageable, meaningful groups.
4. No artificial limits on how many errors to report.

Figure 2 shows the difference between a limited error count and an instance-complete result.

Fig. 2: Side-by-side grid showing limited (left) vs. full (right) DRC error reporting. With full results, teams catch every violation up front—not halfway through integration.

Let AI group what matters: From billions of violations to a handful of signals

When your DRC tool delivers billions of errors, you need help figuring out where to start. This is where AI-driven grouping comes in. Tools like Caliber Vision AI analyze how violations are related and clusters them into “Signals” that represent real, actionable debug points—not just line items in a mega-table.

It doesn’t stop there: it finds patterns (“Signatures”) that pop up all across your chip. If one underlying problem causes tons of violations, you can address it directly instead of fixing related design errors everywhere by hand.

Parallel DRC debug while you run—no more waiting around

You shouldn’t have to wait for a DRC job to finish before you start fixing things. With incremental results, you see violations as soon as they’re found—sometimes within minutes after the run begins. Debugging and DRC can finally happen in parallel. Figure 3 illustrates.

Fig. 3: Workflow for parallel DRC closure. Incremental results mean you can start debug while the DRC analysis is still running.

It also means early, catastrophic mistakes don’t stall the whole team for a day. Block owners, chip integrators, everyone can get started on their piece right away instead of wasting time and re-discovering the same issues later.

Clear status, clear progress: Everyone sees what’s going on

With hundreds of important “Signals” per chip, you need to know what’s being handled and what’s still open. In a tool like Calibre Vision AI, teams can set a clear status for each Signal—ignored, assigned, in progress, resolved—and everyone sees it in the tool, not in some spreadsheet or email chain.

This keeps the team on the same page, cuts confusion and helps you focus on what’s blocking closure (not on tracking people’s progress with sticky notes). Figure 4 shows a tool screenshot displaying Signal statuses.

Fig. 4: Status is built into the workflow—nobody has to ask, ‘Is this fixed yet?’

Global filters: Get right to the interesting results

Faced with millions or billions of results, filtering is a must. You can use global filters for rule checks or zoom in (or out) on specific blocks and regions. If you already know a block has a known issue, just hide it so you and your team can focus on what’s left.

Combining filters is easy—and the tool keeps them around, so you don’t need to rebuild your view every session. Results and heatmaps update instantly to help you spot clusters or critical problems and not waste time surfing through irrelevant data. Figure 5 compares the display of 29 different checks through the full design (left) to just 7 of those 29 (right).

Fig. 5: Filters make it manageable; you can ignore noise and spotlight the real blockers.

Straightforward export for handoff and traceability

Design teams always need to hand off results or dive into an export for audit or integration. With a tool like Calibre Vision AI, it’s easy to save and export exactly what’s relevant—signals, checks or even individual violation shapes—and share that with someone else. Export ASCII results in the chip level or individual block context for assignment and review by the responsible owner. This keeps all the context for debugging and you don’t lose the “where, why and how” as issues move between people or teams.

Real-world impact: One customer’s 40-50% turn-around time reduction

The capabilities sound good in theory. But what does this actually mean for a team shipping advanced chips? A leading semiconductor company’s physical verification team—with over two decades of experience across multiple foundries and process nodes—recently evaluated Calibre Vision AI on a custom 3 nm APU design. Their results speak to the real-world value of this approach.

The team had been struggling with DRC runs that generated 600+ million violations from 3,400 different checks even when limiting results per check to manage the file size. It took days to get results, they had to manually navigate a massive ASCII database to find patterns and visualizing violations was painfully slow. Even worse, the limited results caused them to miss systematic issues.

They used Calibre Vision AI. Between the file size compression, pattern recognition and efficient visualization, they achieved 40–50% reduction in DRC iteration cycle time. After adding in newer features like incremental DRC output, global filtering, hierarchical signature grouping and integrated waiver flow, the team reached 70–80% improvement—a 4–5x speedup over their original methods.

The bottom line: DRC closure that actually fits modern chips

The key capabilities for an advanced DRC analysis and debug platform include:

• The ability to collect every DRC violation across the full chipincluding all blocks, hierarchical levels and repeated instances (this is called “instance-complete” analysis).
• The use of artificial intelligence to group related violations into manageable “Signals” and highlight recurring patterns called “Signatures.” This helps teams quickly spot what’s causing the biggest issues and where to focus effort.
• A real-time, interactive environment where violations load and can be debugged as soon as they’re found, instead of forcing teams to wait for an entire DRC job to finish.
• Support for collaboration, workflow tracking and filtering so teams can coordinate efficiently, filter out noise, assign work and keep track of what’s resolved.

Put these advances together—instance-complete reporting, AI-powered grouping, real-time debug, persistent workflow and powerful filters—and teams can finally keep up with the complexity of today’s SoCs. Debug isn’t a slow, serial process anymore. It’s more efficient, more connected and a lot less painful.

With this new advanced debug platform for physical verification, DRC isn’t just a challenge you struggle through—it’s an organized process you can actually manage and, maybe, even get ahead of.

See more details in my white paper: From billions of violations to actionable insights: Calibre Vision AI | Siemens.